Fin field-effect transistor (FinFET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. A FinFET device can be built on a semiconductor substrate, where a semiconductor material, such as silicon, is patterned into fin-like shapes and functions as the channels of the transistors. Known FinFET devices include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to a substrate) between source/drain regions at opposite ends of the fins in the horizontal direction. As horizontal devices are scaled down, there is reduced space for metal gate and source/drain contacts, which leads to degraded short-channel control and increased middle of the line (MOL) resistance.
Vertical field effect transistors (VFETs) are becoming viable device options for semiconductor devices, for example, complementary metal oxide semiconductor (CMOS) devices, beyond 5 nanometer (nm) node. VFET devices include fin channels with source/drain regions at ends of the fin channels on top and bottom sides of the fins. Current runs through the fin channels in a vertical direction (e.g., perpendicular to a substrate), for example, from a bottom source/drain region to a top source/drain region. Vertical transport architecture devices are designed to extend the product value proposition beyond conventional plateaus and address the limitations of horizontal device architectures by, for example, decoupling of gate length from the contact gate pitch, providing a FinFET-equivalent density at a larger contacted poly pitch (CPP), and providing lower MOL resistance.
Conventional VFETs have a drawback of high parasitic resistance at the top junction between the fin channel and top source/drain region, which can be attributed to a small conduction path at the top of the fin. More specifically, due to oxidation consuming upper portions of the fins during processing, fins in conventional VFETs have a tapered shape, with a larger width at a bottom of the fin and a smaller width at the top of the fin. This is especially true in the case of silicon germanium (SiGe) fins, which are more easily oxidized than silicon fins during thermal processing after fin formation. The smaller width at the top of the fin results in the small conduction path at the top of the fin. Conventional VFETs also suffer from gate-induced drain leakage (GIDL), which is a leakage current caused by a high electric field between gate and drain regions, low dopant solubility at source regions and low gate stack reliability.
Accordingly, there is a need for a VFET structure that reduces parasitic resistance and GIDL, and increases source dopant solubility and gate stack reliability.